The present invention relates to a digital type electronic computer of the type which is suitable for vector processing and which can execute vector calculation at high speed. This type of computer will be referred to as a "vector processing apparatus" hereinafter.
FIG. 1 shows one example of the FORTRAN program which often is used for scientific and technical calculation. According to the program shown in FIG. 1, the storing operation in relation to array data A, B is effected as follows (A(0)+A(1)+A(2)) * 0.33 is stored in B(1) (A(1)+A(2)+A(3)) * 0.33 is stored in B(2) (A(2)+A(3)+A(4)) * 0.33 is stored in B(3) . . . (A(98)+A(99)+A(100)) * 0.33 is stored in B(99) (A(99)+A(100)+A(101)) * 0.33 is stored in B(100).
More specifically, processing is carried out in regard to the first element in the array A in such a manner that the element A(I), the element A(I-1) which immediately precedes the element A(I) and the element A(I+1) which immediately follows the element A(I) are added together and are multiplied by 0.33 (divided by 3). This type of calculation is used in the type of processing where, for example, in a particle simulation, particles are made to correspond to respective elements in the array A, and the state of a particular particle A(I) after a predetermined time has passed is calculated from the present state of a particle A(I-1) and a particle A(I+1) which are respectively immediately in front of and behind the particle A(I). This type of calculation frequently is used in scientific and technical applications. Although the array may be two-dimensional or three-dimensional according to problems to be solved by scientific and techincal calculation, consideration will be herein given to a one-dimensional array such as that shown in FIG. 1 in order to facilitate explanation.
A typical conventional vector processing apapratus has vector registers which temporarily hold vector data and is arranged such that the vector data in a main memory is read out therefrom at high speed, is first stored in the vector registers, is then read out from the vector registers at high speed and is delivered to pipeline calculators, thereby allowing the vector data calculation to be processed at high speed.
FIG. 2 is an illustration schematically showing the arrangement of a vector processing apparatus employed for the program shown in FIG. 1. In FIG. 2, the reference numeral 101 denotes a main memory, while the reference numerals 102 to 104 represent load and store circuits which control the data transfer between the main memory and a plurality of vector registers forming a vector register group, which is constituted by a total of (N+1) vector registers numbered from 0 to N in the example shown in FIG. 2. Each vector register has the function to hold as a block a plurality of elements of vector data, for example, 256 elements of data. The reference numerals 108, 109 represent adders of a pipeline structure which add the data read out from vector registers by means of pipelining and write the results of addition into a selected vector register. The reference numeral 110 denotes a multiplier having a pipeline structure which is similar to the pipelining structure of adders 108, 109 except that the multiplier and the adders differ from each other in the type of calculation performed. The reference numeral 105 denotes a switching circuit which controls the connecting relationship between the (N+1) vector registers and the calculators 108 to 109. It is to be noted that the respective numbers of the load and store circuits, the vector registers, the adders and the multiplier provided in the vector processing apparatus shown in FIG. 2 are not critical.
The FORTRAN program shown in FIG. 1 may be processed in the vector processing apparatus shown in FIG. 2, for example, as follows:
1. The switching circuit 105 is controlled such that the load and store circuits 102, 103 and 104 are respectively connected to the vector register No. 0 (VR0), No. 1 (VR1) and No. 2 (VR2).
2. The load and store circuit 102 is employed to load the vector data A(I-1) into the vector registers VR0 in the order, A(0), A(1), . . . , A(99). Similarly, the load and store circuit 103 is employed to load the vector data A(1) into the vector register VR1 in the order, A(1), A(2), A(3), . . . , A(100), and the load and store circuit 104 is employed to load the vector data A(I+1) into the vector register in the order, A(2), A(3), . . . , A(101).
3. The switching circuit 107 is controlled such that the vector registers VR0, VR1, VR3 are connected to the pipeline adder 108, while the vector registers VR2, VR3, VR4 are connected to the pipeline adder 109.
4. The vector data A(I-1) is successively read out from the vector register VR0, while the vector data A(I) is successively read out from the vector register VR1, and the read out data is supplied to the pipeline adder 108 in which A(I-1)+A(I) is calculated, and the result of the calculation is written into the vector register VR3.
5. The vector data A(I+1) is successively read out from the vector register VR2, while the result of the calculation of A(I-1)+A(I) is successively read out from the vector register VR3, and the read-out data is supplied to the pipeline adder 109 where A(I-1)+A(I)+A(I+1) is calculated, and the result of the calculation is written into the vector register VR4.
6. Then, the result of the calculation of A(I-1)+A(I)+A(I+1) is read out from the vector register VR4 and is supplied to the pipeline multiplier 110 where the read-out value is multiplied by the value 0.33, and the result of the multiplication is stored in the main memory. This procesing step (6) is, however, not directly related to the present invention; therefore, a more detailed description thereof is omitted.
In the case of processing the FORTRAN program shown in FIG. 1 in the conventional vector processing apparatus shown in FIG. 2, almost all of the vector element data of the three vectors, that is, the vector A(I-1) loaded into the corresponding vector register in the order, A(0), A(1), . . . , A(99), the vector A(I) loaded into the corresponding vector register in the order, A(1), A(2), . . . , A(100), and the vector A(I+1) loaded into the corresponding vector register in the order, A(2), A(3), . . . , A(101) overlap one another with only the top vector elements thereof being different from each other. FIG. 3 shows how the respective vectors overlap one another. Thus, the conventional vector processing apparatus has the following problems.
When the three vectors A(I-1), A(I), A(I+1) are to be loaded, three load and store circuits 102 to 104 shown in FIG. 2 are required to load the 98 vector data elements A(2) to A(99), and therefore, contention may arise when these elments are read out from the main memory, resulting in a reduction in the reading rate. The utilization ratio of the load and store circuits is unfavorably low, since three loading and storing circuits are employed to load the three vectors in which almost all the data elements overlap one another.